The present invention relates to a semi conductor device and a technology effectively applicable to, for example, a semiconductor device provided with a circuit for transmitting signals at high speed.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2003-273273) describes a semiconductor device in which a characteristic impedance is adjusted by a thickness of an insulating layer located between a wiring for transmitting signals and a plane layer.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2008-311682) and Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2009-4809) describe a structure in which a plurality of through conductors supplied with ground potential are arranged around a through conductor coupled to a wiring for transmitting differential signals.
Patent Document 4 (Japanese Unexamined Patent Application Publication No. 2013-239511) describes a structure of a wiring board in which a plurality of dielectric layers different in dielectric loss tangent are disposed between ground layers opposed to each other with a wiring for transmitting differential signals in between.